Polycrystalline silicon (poly-Si) thin film has lately attracted considerable attention due to its special physical properties and low cost in thin film transistor (TFT) fabrication, especially in the application of thin film transistor liquid crystal displays (TFT-LCD).
Because poly-Si is an aggregate of single crystal grains and there are thus many grain boundaries, the electrical performance of poly-Si is better than that of amorphous silicon (a-Si) but worse than that of single crystalline silicon. Therefore, grain size enlargement and grain boundaries reduction for poly-Si are very important for improving device performance. The field of display technology is highly focused on development of a flat panel display with higher performance, and thus the electrical performance of poly-Si thin film transistors needs to be improved.
The conventional methods for fabricating poly-Si film are solid phase crystallization (SPC) and direct chemical vapor phase deposition (CVD), but SPC is not applicable to flat panel display fabrication because the upper-limit process temperature of a glass substrate is 650° C., and the grain size of poly-Si is as small as 100 nm in SPC and CVD, therefore the performance of poly-Si film is limited. Besides, metal induced lateral crystallization (MILC) is also used, but the quality of the poly-Si film is affected by metal diffusion issues.
The excimer laser annealing (ELA) method is currently the most commonly used poly-Si film fabrication method. In ELA, the grain size of poly-Si is about 300–600 nm, and the carrier mobility of poly-Si film can reach to 200 cm2/V-s. However, ELA is still not sufficient for future flat panel displays with high performance. Besides, the grain location and order are not uniform because of irregular laser energy deviation, and the electrical performance of devices, such as carrier mobility and uniformity of threshold voltage (Vth), is decreased.
The characteristics of poly-Si devices depend on the quality of poly-Si film; crystal grain size affects the carrier mobility directly. The existence of grain boundaries and rough surface of poly-Si film resulting from crystallization all lead to a rise in Vth and leakage current, and a decrease in carrier mobility and device stability. Therefore, in addition to trying to enlarge the crystal grain size, grain location and grain order control are also ways of decreasing the grain boundary effect in channels for improving device performance.